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IS31AP2111 integrated silicon solution, inc. ? www.issi.com 1 rev. 0 a, 09/ 10 /2014 2 20w stereo digital a udio amplifier with 20 bands eq fun ctions preliminary information september 201 4 general description IS31AP2111 is a digital audio amplifier capable of driving a pair of 8 ? , 20w operating at 24v supply without external heat - sink or fan requirement with play music. IS31AP2111 can provide advanced audio processing capabilities, such as volume control, 20 bands speaker eq, audio mixing, 3d surround and dynamic range control (drc). these functions are fully programmable via a simple i2c control interface. robust protection circuits are provided to protect IS31AP2111 from damage due to accidental erroneous operating condition. IS31AP2111 is more tolerant to noise and pvt (process, voltage, and temperature) variation than the analog class - ab or class - d audio amplifier counterpart implemented by analog circuit design. IS31AP2111 is pop free during instantaneous power switch because of its built - in, robust anti - pop circuit. applications ? tv audio ? boom - box, cd and dvd receiver, docking system ? powered speaker ? wireless audio features ? 16/18/20/24 - bits input with i2s, left - alignment and right - alignment data format ? psnr & dr (a - weighting) loudspeaker: 99db (psnr), 104db (dr) @24v ? multiple sampling frequencies (f s ) - 32khz / 44.1khz / 48khz and - 6 4khz / 88.2khz / 96khz and - 128khz / 176.4khz / 192khz ? system clock = 64x, 128x, 192x, 256x, 384x, 512x, 576x, 768x, 1024x fs - 64x~1024x f s for 32khz / 44.1khz / 48khz - 64x~512x f s for 64khz / 88.2khz / 96khz - 64x~256x f s for 128khz / 176.4khz / 192khz ? supply voltage - 3.3v for digital circuit - 10v~26v for loudspeaker driver ? loudspeaker output power for at 24v - 10w 2ch into 8 ? @0. 24 % thd+n for stereo - 20w 2ch into 8? @0. 38 % thd +n for stereo ? sound processing including: - 20 bands parametric speaker eq - volume control (+24db ~ - 103db, 0.125db/step), - dynamic range control (drc) - dual band dynamic range control - power clip ping - 3d surround sound - channel mixing - noise gate with hysteresis window - bass/treble tone control - dc- blocking high - pass filter ? anti - pop design ? short circuit and over - temperature protection ? i2c control interface with selectable device address ? suppo rt hardware and software reset ? internal pll ? lv under - voltage shutdown and hv under - voltage detection ? power saving mode
IS31AP2111 integrated silicon solution, inc. ? www.issi.com 2 rev. 0 a, 09/ 10 /2014 typical ap p l i c at i o n circuit figure 1 typical application circuit ( for b tl stereo , single - ended input ) figure 2 typical applic ation circuit ( economic t ype, m oderate emi s uppression ) note 1 : these capacitors should be placed as close to speaker jack as possible, and their values should be determined according to em i test results. note 2 : when concerning about short - circuit protect ion, it is suggested using the choke with its i dc larger than 5a. note 3: the snubber circuit can be removed while the v cc 20v.
IS31AP2111 integrated silicon solution, inc. ? www.issi.com 3 rev. 0 a, 09/ 10 /2014 pin configuration package pin configuration (top view) e tssop - 24
IS31AP2111 integrated silicon solution, inc. ? www.issi.com 4 rev. 0 a, 09/ 10 /2014 pin description n o. pin description characteristics 1 pdb power down, low active. schmitt trigger ttl input buffer 2 errorb error status, low active. open - drain output 3 s data i2s serial audio data input. schmitt trigger ttl input buffer 4 lrcin left/right clock input (f s ). schmitt trigger ttl input buffer 5 sda i2c serial data. schmitt trigger ttl input buffer 6 scl i2c serial clock input. schmitt trigger ttl input buff er 7 rstb reset, low active. schmitt trigger ttl input buffer 8 d gnd digital ground. 9 d vdd digital power. 10 ad i2c select address. schmitt trigger ttl input buffer 11 mclk master clock input. schmitt trigger ttl input buffer 12 bclk bit clock inp ut (64f s ). schmitt trigger ttl input buffer 13 vccra right channel supply a. 14, 23 nc no connection. 15 out ra right channel output a. 16 gnd r right channel ground. 17 out rb right channel output b. 18 vccrb right channel supply b. 19 vcclb le ft channel supply b. 20 outlb left channel output b. 21 gndl left channel ground. 22 outla left channel output a. 24 vccla left channel supply a. thermal pad connect to gnd.
IS31AP2111 integrated silicon solution, inc. ? www.issi.com 5 rev. 0 a, 09/ 10 /2014 ordering information industrial range: 0 c to +70 c order part no. package qty is31ap 211 1 - z ls1 - tr is31ap 211 1 - zls 1 e ts sop - 24 , lead- free 2500/reel 62 /tube copyright ? 2014 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specification and its products at any time without notice. issi assumes no liability ari sing out of the application or use of any information, products or services described herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before plac ing orders for products . integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the fa ilure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly af fect its safety or effectiveness. products are not authorized for use in such applications unless integrated silicon solution, inc. receives written assurance to its satisfacti on, that: a.) the risk of injury or damage has been minimized; b.) the user assu me all such risks; and c.) potential liability of integrated silicon solution, inc is adequately protected under the circumstances
IS31AP2111 integrated silicon solution, inc. ? www.issi.com 6 rev. 0 a, 09/ 10 /2014 absolute maximum ratings supply for driver stage (vccr, vccl) , v cc - 0.3v ~ + 30 v supply for digital circuit (dvdd) , v dd - 0.3v ~ + 3.6 v input voltage (sda,scl,rstb,pdb ,errorb,mclk, bclk,lrcin,sdata ) , v in - 0.3v ~ + 3.6 v thermal resi stance, ja 32.8 c/w j unction t emperature range , t j 0 c ~ 150 c stor age t emperature r an g e , t stg - 65 c ~ + 150 c esd (hbm) esd (cdm) tbd note: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these a re stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may a ffect device reliability. recommended operating conditions symbol parameter condition min. typ. max. unit v cc supply for driver stage to vccr/l 10 26 v v dd supply for digital circuit 3.15 3.45 v t j junction operating temperature 0 125 c t a ambi ent operating temperature 0 70 c dc electrical characteristics v cc =24 v, t a =25 c , r l =8 ? (unless otherwise noted) . symbol parameter condition min . typ . max . unit i pdh vcc supply current during power down v cc = 24v 4 200 a i pdl dvdd supply current du ring power down v dd = 3.3v 3.6 10 a v uvh under voltage disabled (for dvdd) 2.9 v v uvl under voltage enabled (for dvdd) 2.8 v r ds(on) static drain - to - source on - state resistor, pmos v cc =24v, i d = 500ma 245 m ? static drain - to - source on - state r esistor, nmos 150 i sc channel over - current protection v cc =24v , i d = 500ma (note 1) 5.1 a t s junction temperature for driver shutdown 158 c temperature hysteresis for recovery from shutdown 33 c logic electrical characteristics v ih hi gh level input voltage 2.0 v v il low level input voltage 0.8 v v oh high level output voltage 2.4 v v ol low level output voltage 0.4 v c in input capacitance 6.4 pf note 1 : loudspeaker over - current protection is only effective when loudsp eaker drivers are properly connected with external lc filters. please refer to the application circuit example for recommended lc filter configuration.
IS31AP2111 integrated silicon solution, inc. ? www.issi.com 7 rev. 0 a, 09/ 10 /2014 ac electrical characteristics t a =25c, v cc = 24 v, v dd = 3.3v, f s = 48khz, r l =8 ? with passive lc lowpass filter (l= 22h, r dc = 0. 12? , c= 470nf), input is 1khz sinewave, volume is 0db unless otherwise specified. symbol parameter condition min . typ . max . unit p o rms o utput power thd+n=0. 38 %, +8db volume (note 2 ) 20 w thd+n total harmonic distortion + noise p o = 10w 0 .24 % v no output noise 20hz ~ 20khz (note 3 ) 179 v snr signal - to - noise ratio +8db volume, input level is - 9db (note 3 ) 99 db dr dynamic range +8db volume, input level is - 68db (note 3 ) 104 db psrr power s upply ripple rejection v rip ple = 1v rms at 1khz - 68 db channel separation 1w @1khz - 85 db i2c digital input switching characteristics (note 4 ) symbol parameter standard mode fast mode unit min. max. min. max. f scl serial - clock f requency 0 100 0 400 khz t buf bus f ree t i me b etween a stop and a start c ondition 4.7 1.3 s t hd, sta hold t ime ( r epeated) start c ondition 4.0 0.6 s t su, sta repeated start c ondition s etup t ime 4.7 0.6 s t su, sto stop c ondition s etup t ime 4.0 0.6 s t hd, dat data h old t ime 0 3.4 5 0 0.9 s t su, dat data s etup t ime 250 100 ns t low scl c lock l ow p eriod 4.7 1.3 s t high scl c lock h igh p eriod 4.0 0. 6 s t r rise t ime of b oth sda and scl s ignals, r eceiving 1000 20+0.1c b 300 ns t f fall t ime of b oth sda and scl s ignals, r e ceiving 300 20+0.1c b 300 ns c b capacitive load for each bus line 400 400 pf v nl noise margin at the low level for each connected device (including hysteresis) 0.1v dd 0.1v dd v v nh noise margin at the high level for each connected device (including hysteresis) 0.2v dd 0.2v dd v
IS31AP2111 integrated silicon solution, inc. ? www.issi.com 8 rev. 0 a, 09/ 10 /2014 i2s digital input switching characteristics (note 4 ) symbol parameter condition min . typ . max . unit t lr lrc in period (1/f s ) 10.41 31.25 s t bl bclk rising edge to lrc in edge 50 ns t lb lrc in edge to bclk rising edge 50 ns t bcc bclk period (1/64f s ) 162.76 488.3 ns t bch bclk pulse width high 81.38 244 ns t bcl cblk pulse width low 81.38 244 ns t ds sdata set up time 50 ns t dh sdata hold time 50 ns note 2 : thermal dissipation is limited by package type and pcb design. the external heat - sink or system cooling method should be adopted for maximum power output. note 3 : measured with a - weighting filter. note 4 : guaranteed by design. figure 3 i2c timing figure 4 i2s figure 5 left - alignment
IS31AP2111 integrated silicon solution, inc. ? www.issi.com 9 rev. 0 a, 09/ 10 /2014 figure 6 right - alignment figure 7 system clock timing figure 8 timing relationship (using i2s format as an example)
IS31AP2111 integrated silicon solution, inc. ? www.issi.com 10 rev. 0 a, 09/ 10 /2014 typical performance characteristics figu re 9 thd+n vs. output power figure 11 frequency response figure 13 spectrum at peak snr at - 1db signal input figure 10 thd+n vs. frequency figure 12 cross - t alk figure 14 spectrum at - 60db signal input level
IS31AP2111 integrated silicon solution, inc. ? www.issi.com 11 rev. 0 a, 09/ 10 /2014 figure 15 efficiency vs. tota l output power (without power saving mode) figure 1 7 thd +n vs. output power figure 16 efficiency vs. total output power (with power saving mode)
IS31AP2111 integrated silicon solution, inc. ? www.issi.com 12 rev. 0 a, 09/ 10 /2014 functional block diagram
IS31AP2111 integrated silicon solution, inc. ? www.issi.com 13 rev. 0 a, 09/ 10 /2014 applications information operation modes without i2c control the d efault settings, bass, treble, eq, volume, drc, ?, and pll are applied to register table content when using IS31AP2111 without i2c control. the more information about default settings, please refer to the highlighted column of register table section. with i2c control when using i2c control, user can program suitable parameters into IS31AP2111 for their specific applications. please refer to the register table section to get the more detail. internal pll IS31AP2111 has a built - in pll internally. the mclk/f s ratio will be fixed at 1024x, 512x, or 256x with a sample frequency of 48khz, 96khz, or 192khz respectively. a career clock frequency is the frequency divided by 128 of master clock. table 1 mclk/f s ratio f s mclk frequency 48khz 49.152mhz 44.1khz 45.158 mhz 32khz 32.768mhz default volume the default volume level of IS31AP2111 is +1.675db, the default volume register table setting is muted. please give a de - mute command via i2c when the whole system is stable. about the more detailed information, please refer to the register table section. reset when the r s tb pin is lowered, IS31AP2111 will clear the stored data and reset the register table to default values. IS31AP2111 will exit reset state at the 256 th mclk cycle after the r s tb pin is raised to high. po wer down control IS31AP2111 has a built - in volume f ade- in/fade - out design for power down and mute function. the relative power down timing diagrams for loudspeakers are shown below. figure 1 8 power d own timing diagrams with mute figure 1 9 p owe r down timing diagrams the volume level will be decreased to - db in several lrc in cycles. once the fade - out procedure is finished, IS31AP2111 will turn off the power stages, stop clock signals (mclk, bclk) from feeding into digital circuit and turn off the current of the internal analog circuits. after pd b pin is pulled low, IS31AP2111 needs t fade time to finish the above works before entering power down state. users can?t program IS31AP2111 during power down state, but all the sett ings of register table will still be kept except that dvdd is removed. if the power down function is disabled in the midway of the fade - out procedure, IS31AP2111 will also execute the fade - in procedure. in addition, IS31AP2111 will establish the analog cir cuits? bias current and feed the clock signals (mclk, bclk) into digital circuits. then, IS31AP2111 will return to its normal operation without power down. pdb pdb pdb pdb
IS31AP2111 integrated silicon solution, inc. ? www.issi.com 14 rev. 0 a, 09/ 10 /2014 self - protection circuits IS31AP2111 has built - in protection circuits including thermal, short - circu it and under - voltage detection circuits. thermal protection when the internal junction temperature is higher than 1 58 c , power stages will be turned off and IS31AP2111 will return to normal operation once the temperature drops to 125 c . the temperature val ues may vary around 10%. short - circuit protection the short - circuit protection circuit protects the output stage when the wires connected to loudspeakers are shorted to each other or gnd/vdd. for normal 24v operations, the current flowing through the power stage will be less than 5.1a for stereo configuration. otherwise, the short - circuit detectors may pull the error b pin to dgnd, disabling the output stages. when the over - temperature or short - circuit condition occurs, the open - drain error b pin will be pull ed low and latched into error state. once the over - temperature or short - circuit condition is removed, IS31AP2111 will exit error state when one of the following conditions is met: (1) rs tb pin is pulled low. (2) pd b pin is pulled low . (3) master mute is e nabled through the i2c interface. under - voltage protec t i on once the v dd voltage is lower than 2.8v, IS31AP2111 will turn off its loudspeaker power stages and cease the operation of dig ital processing circuits. when v dd becomes larger than 2.9v, IS31AP2111 will return to normal operation. anti - pop design IS31AP2111 will generate appropriate control signals to suppress pop sounds during initial power on/off, power down/up, mute, and volume level changes. 3d surround sound IS31AP2111 provides the virtual surro und sound technology with greater separation and depth voice quality for stereo signals. power on sequence hereunder is IS31AP2111 ?s power on sequence. please note that IS31AP2111 default volume setting is muted initially. please give a de - mute command via i2c when the whole system is stable. figure 20 power on sequence
IS31AP2111 integrated silicon solution, inc. ? www.issi.com 15 rev. 0 a, 09/ 10 /2014 table 2 power on sequence symbol condition min. max. unit t1 0 - ms t2 0 - ms t3 10 - ms t4 0 - ms t5 10 - ms t6 10 - ms t7 0 - ms t8 200 - ms t9 20 - ms t10 - 0. 1 ms t11 - 0.1 ms t12 25 - ms t13 25 - ms t14 - 22 ms t15 def=l or h - 0.1 ms power off sequence hereunder is IS31AP2111 ?s power off sequence. figure 21 power o ff sequence table 3 power off sequence symbol min. t1 35ms t2 0.1ms t3 0ms t4 1ms t5 1ms
IS31AP2111 integrated silicon solution, inc. ? www.issi.com 16 rev. 0 a, 09/ 10 /2014 i2c - bus transfer protocol introduction IS31AP2111 employs i2c - bus transfer protocol. two wires, serial data and serial clock carry information between the devices connected to the bus. each device is recognized by a unique 7 - bit address and can operate as either a transmitter or a receiver. the master device initiates a data transfer and provides the serial clock on the bus. IS31AP2111 is always an i2c slave device. protocol start a nd stop c ondition start is identified by a high to low t ransition of the sda signal . a start condition must precede any command for data transfer. a stop is identified by a low to high transition of the sda signal. a stop condition terminates communication between IS31AP2111 and the master device on the bus. in both start and stop, the scl is stable in the high state. data v alidity the sda signal must be stable during the high period of the clock. the high or low change of sda only occurs when scl signal is low. IS31AP2111 samples the sda signal at the rising ed ge of scl signal. device a ddressing the master generates 7 - bit address to recognize slave devices. when IS31AP2111 receives 7 - bit address matched with 0110x00 (where x can be selected by external ad pin, respectively), IS31AP2111 will acknowledge at the 9t h bit (the 8th bit is for r/w bit). the bytes following the device identification address are for IS31AP2111 internal sub - addresses. data t ransferring each byte of sda signaling must consist of 8 consecutive bits, and the byte is followed by an acknowledge bit. data is transferred with msb first, as shown in the figure below. in both write and read operations, IS31AP2111 supports both single - byte and multi - byte transfers. refer to the figure below for detailed data - transferring protocol. figure 22 da ta transferring register definitions the IS31AP2111 ?s audio signal processing data flow is shown below. users can control these functions by programming appropriate settings in the register table. in this section, the register table is summarized first. th e definition of each register follows in the next section.
IS31AP2111 integrated silicon solution, inc. ? www.issi.com 17 rev. 0 a, 09/ 10 /2014 dual b and drc enable dual b ands drc disable
IS31AP2111 integrated silicon solution, inc. ? www.issi.com 18 rev. 0 a, 09/ 10 /2014 table 4 register function address name table default 00h state control 1 register 5 000x 0000 01h state control 2 register 6 xx 00 0000 02h st ate control 3 register 7 xxxx 0000 03h master volume control register 8 0001 1000 04h~06h channel 1~3 volume register 9 0001 0100 07h ,08h bass /treble tone register 10 xxx1 0000 09h reserved (note) - - 0ah state control 4 register 11 1001 0000 0bh~0ch channel 1~2 configuration register 12 xxx1 0000 0dh reserved - - 0eh drc limiter attack/release rate register 13 0110 1010 0fh~10h reserved (note) - - 11h state control 5 register 14 xx 11 x 010 12h vcc under voltage selection register 15 1xxx 0001 13h noise gate gain register 16 xxx0 xx00 14h coefficient ram base address register 17 x 000 0000 15h~23h user - defined coefficients register 1 8 ~ 22 - 24h coefficients control register 23 xxxx 0000 25h~29h reserved (note) - - 2ah power saving mode switchin g level register 24 0000 1101 2bh volume fine tune register 25 0011 1111 note: the reserved registers are not allowed to write any bits in them, or the ic will be abnormal. table 5 00h state c ontrol 1 register bit d7:d5 d4 d3 name if - pwml_x default 000 x 0 bit d2 d1 d0 name pwmr_x lv_uvsel lrexc default 0 0 0 IS31AP2111 supports multiple serial data input formats including i2s, left - alignment and right - alignment. these formats are selected by users via d 7~ d 5 of address 00h . the left/right channe ls can be exchanged to each other by programming to address 00h/d 0, lrexc . if input format 0 00 i2s 16 - 24 bits 001 left - alignment 16 - 24 bits 010 right - alignment 16 bits 011 right - alignment 18 bits 100 right - alignment 20 bits 101 right - alignment 24 bits others not available p wml_x out l a/b exchange 0 no exchange 1 exchange p wmr_x outra/b exchange 0 no exchange 1 exchange lv _uvsel lv under voltage selection 0 2.8v 1 3.1v lrexc left/right channel exchanged 0 no exchange 1 left/right e xchange
IS31AP2111 integrated silicon solution, inc. ? www.issi.com 19 rev. 0 a, 09/ 10 /2014 ta ble 6 0 1 h state c ontrol 2 register bit d7:d6 d5:d4 d3:d0 name - fs pmf default xx 00 0000 IS31AP2111 has a built - in pll which can be bypassed by pulling the pll pin high. when pll is bypassed, IS31AP2111 only supports 1024x, 512x and 256x mclk/fs rati o for fs is 32/44.1/48khz, 64/88.2/96khz, and 128/176.4/192khz respectively. when pll is enabled, multiple mclk/fs ratios are supported. detail setting is shown in the following table. fs sampling frequency 00 32/44.1/48khz 0 1 64/88.2/96khz 1x 128/176.4/1 92khz pmf multiple mclk/fs ratio setting (pll is not bypassed) 0000 1024x(fs=00)/ 512x(fs=01)/ 256x(fs=1x) 0001 64x 0010 128x 0011 192x 0100 256x 0101 384x (not available when fs=1x) 0110 512x (not available when fs=1x) 0111 576x (not available when fs=0 1,1x) 1000 768x (not available when fs=01,1x) 1001 1024x (not available when fs=01,1x) others not available note: the fs pmf should be lower than 49.152mhz, or the system will be error. table 7 0 2 h state c ontrol 3 register bit d7:d 4 d3 d 2 :d0 name - m ute cm1:cm3 default xxxx 0 000 IS31AP2111 has mute function including master mute and channel mute. when master mute is enabled, all 3 processing channels are muted. user can mute these 3 channels individually by channel mute. when the mute function is e nabled or disabled, the fade - out or fade - in process will be initiated. mute master mute 0 all channel not muted 1 all channel muted cmx channel x mute 0 channel x not muted 1 channel x muted table 8 0 3 h master volume control register bit d7:d0 name mv default 0001 1000 IS31AP2111 support s both master - volume ( 03h register ) and ch annel - volume control ( 04 h, 05h and 06h register s ) modes. both volume control settings range from +12db ~ - 103db and 0.5db per step. note that the master volume control is adde d to the individual channel volume control as the total volume control. for example, if the master volume level is set at, level a (in db unit) and the channel volume level is set at level b (in db unit), the total volume control setting is equal to level a plus with level b. - 103db Q total volume ( level a + level b ) Q +24db. mv master volume 0000 0000 +12.0db 0000 000 1 +11.5db 0000 0010 +11.0db ? 0001 1000 0db ? 1110 0110 - 103.0db 1110 0111 - others - table 9 0 4 h ~06h channel 1 ~3 v olume register s bit d7:d0 name c x v default 0001 0100 c x v channel x volume 0000 0000 +12.0db 0000 000 1 +11.5db ? 0001 0100 +2db ? 1110 0110 - 103.0db 1110 0111 - others - table 10 0 7 h / 08h bass/treble t one register s bit d7:d5 d6:d0 name - btc/ttc default xxx 10000 last two sets of eq can be programmed as bass/treble tone boost and cut. when, 0ah r egister, d 6, bte is set to high, the eq - 8 and eq - 9 will
IS31AP2111 integrated silicon solution, inc. ? www.issi.com 20 rev. 0 a, 09/ 10 /2014 perform as bass and treble respectively. the - 3db corner frequency of bass is 360hz, and treble is 7khz. the gai n range for both filters is +12db ~ - 12db with 1db per step. btc/ttc bass/treble gain setting 00000 +12db ? 00100 +12db 00101 +11db ? 10000 0db 10001 - 1db ? 111xx - 12db table 11 0 ah state c ontrol 4 register bit d7 d6 d5 d4 name s rbp bte tbdrce n g e default 1 0 0 1 bit d3 d2 d1 d0 name eq l ps l dspb hp b default 0 0 0 0 the IS31AP2111 provides several dsp setting as following. s r b p surround bypass 0 surround enable 1 surround bypass bte bass/treble selection bypass 0 bass/treble disable 1 bass /treble enable tbdrce two band drc enable 0 two band drc disable 1 two band drc enable ng e noise gate enable 0 noise gate disable 1 noise gate enable eq l eq link 0 each channel uses individual eq 1 channel - 2 uses channel - 1 eq psl post - scale link 0 each channel uses individual post - scale 1 use channel - 1 post - scale dspb eq bypass 0 eq enable 1 eq bypass hp b dc blocking hpf bypass 0 hpf dc enable 1 hpf dc bypass table 12 0 b h ~0ch channel 1~2 c onfiguration register s bit d7:d5 d4 d3 name - cxdrcm cxpc bp default xxx 1 0 bit d2 d1 d0 name cxdrcbp - cxvbp default 0 x 0 the IS31AP2111 can configure each channel to enable or bypass drc and channel volume and select the limiter set. IS31AP2111 support two mode of drc, rms and peak detection which can be selected via d 4. cxdrcm channel 1/2 drc mode 0 peak detection 1 rms detection cxpcbp channel 1/2 power clipping bypass 0 channel 1/2 pc enable 1 channel 1/2 pc bypass cxdrcbp channel 1/2 drc bypass 0 channel 1/2 drc enable 1 channel 1/2 drc bypas s cxvbp channel 1/2 volume bypass 0 channel 1/2?s master volume operation 1 channel 1/2?s master volume bypass table 1 3 0 eh drc limiter attack/release rate register bit d7:d5 d6:d0 name la lr default 0110 1010 the IS31AP2111 defines a set of limite r. the attack/release rates are defines as following table. la drc attack rate 0000 3db/ms 0001 2.667db/ms
IS31AP2111 integrated silicon solution, inc. ? www.issi.com 21 rev. 0 a, 09/ 10 /2014 0010 2.182db/ms 0011 1.846db/ms 0100 1.333db/ms 0101 0.889db/ms 0110 0.4528db/ms 0111 0.2264db/ms 1000 0.15db/ms 1001 0.1121db/ms 1010 0.0902db/ms 1 011 0.0752db/ms 1100 0.0645db/ms 1101 0.0563db/ms 1110 0.0501db/ms 1111 0.0451db/ms lr drc release rate 0000 0.5106 db/ms 0001 0.1371 db/ms 0010 0.0743 db/ms 0011 0.0499 db/ms 0100 0.0360 db/ms 0101 0.0299 db/ms 0110 0.0264 db/ms 0111 0.0208 db/ms 1000 0.0198 db/m s 1001 0.0172 db/ms 1010 0.0147 db/ms 1011 0.0137 db/ms 1100 0.0134 db/ms 1101 0.0117 db/ms 1110 0.0112 db/ms 1111 0.0104 db/ms table 1 4 11h state c ontrol 5 register bit d7:d6 d5 d4 d3 name - sw_rstb lvuv_fade - default xx 1 1 x bit d2 d1 d0 name dis_mclk_ det qt_en pwm_sel default 0 1 0 the IS31AP2111 provides several dsp setting as following. sw_rstb software reset 0 reset 1 normal operation lvuv_fade low under voltage fade 0 no fade 1 fade dis_mclk_det disable mclk detect circuit 0 enable mclk detect circuit 1 disable mclk detect circuit qt_en power saving mode 0 disable 1 enable pwm_sel pwm modulation 0 qua - ternary 1 ternary table 1 5 12h vcc under voltage selection register bit d7 d6:d4 d3:d0 name dis_hvuv - hv_uvsel default 1 xxx 0001 IS31AP2111 can disable hv under voltage detection via d 7. IS31AP2111 support multi - level hv under voltage detection via d 3~ d 0, using this function, IS31AP2111 will fade out signal to avoid pop sounds if high voltage supply disappear before low volta ge supply. dis_hvuv disable hv under voltage selection 0 enable 1 disable hv_uvsel uv detection level 0000 8.2v 0001 9.7v 0011 13.2v 0100 15.5v 1100 19.5v others 9.7v table 1 6 13h noise gate gain register bit d7:d5 d4 name - dis_ng_fade defa ult xxx 0 bit d3:d2 d1:d0 name - ng_gain default xx 00 IS31AP2111 provide noise gate function if receiving 2048 signal sample points smaller than noise gate attack level. user can change noise gate gain via d 1~ d 0. when noise gate function occurs, inpu t signal will multiply noise gate gain (x1/8, x1/4 x1/2, x0). user can select fade out or not via d 4.
IS31AP2111 integrated silicon solution, inc. ? www.issi.com 22 rev. 0 a, 09/ 10 /2014 dis_ng_fade disable noise gate fade 0 fade 1 no fade ng_gain noise gate gain 00 x1/8 01 x1/4 10 x1/2 11 mute table 1 7 14h coefficient ram base a ddress register bit d7 d6:d0 name - cfa default x 000 0000 an on - chip ram in IS31AP2111 stores user - defined eq and mixing coefficients. the content of this coefficient ram is indirectly accessed via coefficient registers, which consist of one base addre ss register (14 h ), fi ve sets of registers ( 15 h ~ 23 h ) of three consecutive 8 - bit entries for each 24 - bit coefficient, and one control register (24 h ) to control access of the coefficients in the ram. cfa coefficient ram base address table 1 8 15h ~17h use r - defined coefficients register s ( top/middle/bottom 8 - bits of coefficients a1 ) bit d7:d0 name c1b default - table 19 18h ~1ah user - defined coefficients register s ( top/middle/bottom 8 - bits of coefficients a 2 ) bit d7:d0 name c2b default - table 2 0 1b h ~1dh user - defined coefficients register s ( top/middle/bottom 8 - bits of coefficients a1 ) bit d7:d0 name c3b default - table 2 1 1e h ~20h user - defined coefficients register s ( top/middle/bottom 8 - bits of coefficients b2 ) bit d7:d0 name c4b default - table 2 2 21h ~23h user - defined coefficients register s ( top/middle/bottom 8 - bits of coefficients a 0 ) bit d7:d0 name c5b default - table 2 3 24h coefficients c ontrol register bit d7:d4 d3 d2 d1 d0 name - ra r1 wa w1 default xxxx 0 0 0 0 ra enab le of reading a set of coefficients from ram 0 read complete 1 read enable r1 enable of reading a single coefficients from ram 0 read complete 1 read enable wa enable of writing a set of coefficients to ram 0 write complete 1 write enable w1 enable of writing a single coefficient to ram 0 write complete 1 write enable table 2 4 2ah power saving mode switching level register bit d7 :d5 d 4 :d0 name qt_sw_window qt_sw_level default 000 01101 if the pwm exceeds the programmed switching power level (defau lt 26 40ns), the modulation algorithm will change from quaternary into power saving mode. it results in higher power efficiency during larger power output operations. if the pwm drops below the programmed switching power level - power saving mode hysteresi s window, the
IS31AP2111 integrated silicon solution, inc. ? www.issi.com 23 rev. 0 a, 09/ 10 /2014 modulation algorithm will change back to quaternary modulation. qt_sw_window power saving mode hysteresis window 000 2 001 3 010 4 011 5 100 6 101 7 110 8 111 9 qt_sw_level switching level 00000 4 00001 4 00010 6 ? 01101 26 ? 11111 62 ta ble 2 5 2b h volume fine tune register bit d7:d 6 d5: d4 d3:d2 d1:d0 name mv _ft c1v _ft c2v _ft - default 00 11 11 11 IS31AP2111 supports both master - volume fine tune and channel - volume control fine tune modes. both volume control settings range from 0db ~ - 0.375db and 0.125db per step. note that the master volume fine tune is added to the individual channel volume fine tune as the total volume fine tune. mv _ft master volume fine tune 00 0db 01 - 0.125db 10 - 0.25db 11 - 0.375db c1v _ft channel 1 volume f ine tune 00 0db 01 - 0.125db 10 - 0.25db 11 - 0.375db c 2 v _ft channel 2 volume fine tune 00 0db 01 - 0.125db 10 - 0.25db 11 - 0.375db ram access the procedure to read/write coefficient(s) from/to ram is as followings: read a single coefficient from ram : 1. write 7 - bit of address to i2c address - 0x14 2. write 1 to r1 bit in address - 0x24 3. read top 8 - bits of coefficient in i2c address - 0x15 4. read middle 8 - bits of coefficient in i2c address - 0x16 5. read bottom 8 - bits of coefficient in i2c address - 0x17 rea d a set of coefficients from ram: 1. write 7 - bits of address to i2c address - 0x14 2. write 1 to ra bit in address - 0x24 3. read top 8 - bits of coefficient a1 in i2c address - 0x15 4. read middle 8 - bits of coefficient a1in i2c address - 0x16 5. read bottom 8 - bits of coefficient a1 in i2c address - 0x17 6. read top 8 - bits of coefficient a2 in i2c address - 0x18 7. read middle 8 - bits of coefficient a2 in i2c address - 0x19 8. read bottom 8 - bits of coefficient a2 in i2c address - 0x1a 9. read top 8 - bits of coefficient b1 in i 2c address - 0x1b 10. read middle 8 - bits of coefficient b1 in i2c address - 0x1c 11. read bottom 8 - bits of coefficient b1 in i2c address - 0x1d 12. read top 8 - bits of coefficient b2 in i2c address - 0x1e 13. read middle 8 - bits of coefficient b2 in i2c address - 0x1f 14. read bottom 8 - bits of coefficient b2 in i2c address - 0x20 15. read top 8 - bits of coefficient a0 in i2c address - 0x21 16. read middle 8 - bits of coefficient a0 in i2c address - 0x22 17. read bottom 8 - bits of coefficient a0 in i2c address - 0x23 write a single coefficient from ram: 1. write 7 - bis of address to i2c address - 0x14 2. write top 8 - bits of coefficient in i2c address - 0x15 3. write middle 8 - bits of coefficient in i2c address - 0x16 4. write bottom 8 - bits of coefficient in i2c address - 0x17 5. write 1 to w1 bit in address - 0x24
IS31AP2111 integrated silicon solution, inc. ? www.issi.com 24 rev. 0 a, 09/ 10 /2014 write a set of coefficients from ram: 1. write 7 - bits of address to i2c address - 0x14 2. write top 8 - bits of coefficient a1 in i2c address - 0x15 3. write middle 8 - bits of coefficient a1 in i2c address - 0x16 4. write bottom 8 - bits of coef ficient a1 in i2c address - 0x17 5. write top 8 - bits of coefficient a2 in i2c address - 0x18 6. write middle 8 - bits of coefficient a2 in i2c address - 0x19 7. write bottom 8 - bits of coefficient a2 in i2c address - 0x1a 8. write top 8 - bits of coefficient b1 in i2c address - 0x1b 9. write middle 8 - bits of coefficient b1 in i2c address - 0x1c 10. write bottom 8 - bits of coefficient b1 in i2c address - 0x1d 11. write top 8 - bits of coefficient b2 in i2c address - 0x1e 12. write middle 8 - bits of coefficient b2 in i2c address - 0x1f 13. write bottom 8 - bits of coefficient b2 in i2c address - 0x20 14. write top 8 - bits of coefficient a0 in i2c address - 0x21 15. write middle 8 - bits of coefficient a0 in i2c address - 0x22 16. write bottom 8 - bits of coefficient a0 in i2c address - 0x23 17. write 1 to wa bit in address - 0x24 note: the read and write operation on ram coefficients works only if lrc in (pin 15) switching on rising edge. and, before each writing operation, it is necessary to read the address - 0x24 to confirm whether ram is writable curren t in first. if the logic of w1 or wa is high, the coefficient writing is prohibited. user - defined equalizer the IS31AP2111 provides 18 parametric equalizer (eq). users can program suitable coefficients via i2c control interface to program the required audi o band frequency response for every eq. the transfer function the data format of 2?s complement binary code for eq coefficient is 3.21. i.e., 3 - bits for integer (msb is the sign bit) and 21 - bits for mantissa. each coefficient range is from 0x800000 ( - 4) to 0x7fffff (+3.999999523). these coefficients are stored in user defined ram and are referenced in following manner: chxeqya0=a0 chxeqya1=a1 chxeqya2=a2 chxeqyb1= - b1 chxeqyb2= - b2 where x and y represents the number of channel and the band number of eq equalizer. all user - defined filters are path - through, where all coefficients are defaulted to 0 after being powered up, except the a0 that is set to 0x200000 which represents 1. mixer the IS31AP2111 provides mixers to generate the extra audio source from the input left and right channels. the coefficients of mixers are defined in range from 0x800000 ( - 1) to 0x7fffff (0.9999998808). the function block diagram is as following figure : figure 2 3 mixer function block diagram pre - scale for each audio channel, IS31AP2111 can scale input signal level prior to eq processing which is realized by a 24- bit signed fractional multiplier. the pre - scale factor, ranging from - 1 (0x800000) to 0.9999998808 (0x7fffff), for this multiplier, can be loaded i nto ram. the default values of the pre - scaling factors are set to 0x7fffff. programming of ram is described in ram access. post - scale the IS31AP2111 provides an additional multiplication after equalizing and before interpolation stage, which is realized by a 24 - bit signed fractional multiplier. the post - scaling factor, ranging from - 1 (0x800000) to 0.9999998808 (0x7fffff), for this multiplier, can be loaded into ram. the default values of the post - scaling factors are set to 0x7fffff. all channels can use th e channel - 1 post - scale factor by setting the post - scale link. programming of ram is described in ram access.
IS31AP2111 integrated silicon solution, inc. ? www.issi.com 25 rev. 0 a, 09/ 10 /2014 power clipping the IS31AP2111 provides power clipping function to avoid excessive signal that may destroy loud speaker. the power clipping level i s defined by 24 - bit representation and is stored in ram address 0x6f and 0x70. the following table shows the power clipping level?s numerical representation. table 2 6 sample calculation for power clipping max. amplitude db linear decimal hex (3.21 format) v cc 0 1 2097152 200000 v cc 0.707 - 3 0.707 1484574 16a71e v cc 0.5 - 6 0.5 1048576 100000 v cc l x l= 10 (x/20) d= 2097152 l h= dec2hex(d) attack threshold for dynamic range control (drc) the IS31AP2111 provides dynamic range control (drc) function. when t he input exceeds the programmable attack threshold value, the output power will be limited by this threshold power level via gradual gain reduction. attack threshold is defined by 24 - bit representation and is stored in ram address 0x71 and 0x72. release th reshold for dynamic range control (drc) after IS31AP2111 has reached the attack threshold, its output power will be limited to that level. the output power level will be gradually adjusted to the programmable release threshold level. release threshold is d efined by 24 - bit representation and is stored in ram address 0x73 and 0x74. the following table shows the attack and release threshold?s numerical representation. table 2 7 sample calculation for attack and release threshold power db linear decimal hex (3. 21 format) ( v cc ^ 2 )/r 0 1 2097152 200000 ( v cc ^ 2 )/2r - 3 0.5 1048576 100000 ( v cc ^ 2 )/4r - 6 0.25 524288 80000 ( v cc ^ 2 )/r l x l= 10 ( x/1 0) d= 2097152 l h= dec2hex(d) to best illustrate the dynamic range control, please refer to the following figure. fig ure 2 4 attack and release threshold
IS31AP2111 integrated silicon solution, inc. ? www.issi.com 26 rev. 0 a, 09/ 10 /2014 noise gate attack level when both left and right signals have 2048 consecutive sample points less than the programmable noise gate attack level, the audio signal will multiply noise gate gain, which can be set at x1/8 , x1/4, x1/2, or zero if the noise gate function is enabled. noise gate attack level is defined by 24 - bit representation and is stored in ram address 0x75. noise gate release level after entering the noise gating status, the noise gain will be removed when ever IS31AP2111 receives any input signal that is more than the noise gate release level. noise gate release level is defined by 24 - bit representation and is stored in ram address 0x76. the following table shows the noise gate attack and release threshold level?s numerical representation. table 2 8 sample calculation for noise gate attack and release level input amplitude linear decimal hex (1.23 format) 0db 1 8388607 7fffff - 100db 10 - 5 83 53 - 110db 10 - 5.5 26 1a xdb l= 10 ( x/2 0) d= 2097152 l h= dec2hex (d) drc energy coefficient figure 2 5 digital processing of calculating rms signal power the above figure illustrates the digital processing of calculating rms signal power. in this processing, a drc energy coefficient is required, which can be progra mmed for different frequency range. energy coefficient is defined by 24 - bit representation and is stored in ram address 0x77 and 0x78. the following table shows the drc energy coefficient numerical representation. table 29 sample calculation for drc energ y coefficient drc energy coefficient db linear decimal hex ( 1.23 format) 1 0 1 8388607 7fffff 1/256 - 48.2 1/256 524288 80000 1/1024 - 60.2 1/1024 131072 20000 l x l= 10 ( x/2 0) d= 2097152 l h= dec2hex(d)
IS31AP2111 integrated silicon solution, inc. ? www.issi.com 27 rev. 0 a, 09/ 10 /2014 the u ser d efined ram the contents of user defin ed ram is represented in following table. table 30 user defined ram address name coefficient default address name coefficient default 0x00 channel 1 eq1 ch1eq1a1 0x000000 0x32 channel 2 eq1 ch2eq1a1 0x000000 0x01 ch1eq1a2 0x000000 0x33 ch2eq1a2 0x000 000 0x02 ch1eq1b1 0x000000 0x34 ch2eq1b1 0x000000 0x03 ch1eq1b2 0x000000 0x35 ch2eq1b2 0x000000 0x04 ch1eq1a0 0x200000 0x36 ch2eq1a0 0x200000 0x05 channel 1 eq2 ch1eq2a1 0x000000 0x37 channel 2 eq2 ch2eq2a1 0x000000 0x06 ch1eq2a2 0x000000 0x38 ch2eq2a2 0x000000 0x07 ch1eq2b1 0x000000 0x39 ch2eq2b1 0x000000 0x08 ch1eq2b2 0x000000 0x3a ch2eq2b2 0x000000 0x09 ch1eq2a0 0x200000 0x3b ch2eq2a0 0x200000 0x0a channel 1 eq3 ch1eq3a1 0x000000 0x3c channel 2 eq3 ch2eq3a1 0x000000 0x0b ch1eq3a2 0x000000 0x3d ch2eq3a2 0x000000 0x0c ch1eq3b1 0x000000 0x3e ch2eq3b1 0x000000 0x0d ch1eq3b2 0x000000 0x3f ch2eq3b2 0x000000 0x0e ch1eq3a0 0x200000 0x40 ch2eq3a0 0x200000 0x0f channel 1 eq4 ch1eq4a1 0x000000 0x41 channel 2 eq4 ch2eq4a1 0x000000 0x10 ch1eq4a2 0x000000 0x42 ch2eq4a2 0x000000 0x11 ch1eq4b1 0x000000 0x43 ch2eq4b1 0x000000 0x12 ch1eq4b2 0x000000 0x44 ch2eq4b2 0x000000 0x13 ch1eq4a0 0x200000 0x45 ch2eq4a0 0x200000 0x14 channel 1 eq5 ch1eq5a1 0x000000 0x46 channel 2 eq5 ch2 eq5a1 0x000000 0x15 ch1eq5a2 0x000000 0x47 ch2eq5a2 0x000000 0x16 ch1eq5b1 0x000000 0x48 ch2eq5b1 0x000000 0x17 ch1eq5b2 0x000000 0x49 ch2eq5b2 0x000000 0x18 ch1eq5a0 0x200000 0x4a ch2eq5a0 0x200000 0x19 channel 1 eq6 ch1eq6a1 0x000000 0x4b ch annel 2 eq6 ch2eq6a1 0x000000 0x1a ch1eq6a2 0x000000 0x4c ch2eq6a2 0x000000 0x1b ch1eq6b1 0x000000 0x4d ch2eq6b1 0x000000 0x1c ch1eq6b2 0x000000 0x4e ch2eq6b2 0x000000 0x1d ch1eq6a0 0x200000 0x4f ch2eq6a0 0x200000
IS31AP2111 integrated silicon solution, inc. ? www.issi.com 28 rev. 0 a, 09/ 10 /2014 table 30 user defined ram (continues) address name coefficient default address name coefficient default 0x1e channel 1 eq7 ch1eq7a1 0x000000 0x50 channel 2 eq7 ch2eq7a1 0x000000 0x1f ch1eq7a2 0x000000 0x51 ch2eq7a2 0x000000 0x20 ch1eq7b1 0x000000 0x52 ch2eq7b1 0x000000 0x21 ch1eq7b2 0x000000 0x53 ch2eq7b2 0x000000 0x22 ch1eq7a0 0x200000 0x54 ch2eq7a0 0x200000 0x23 channel 1 eq8 ch1eq8a1 0x000000 0x55 channel 2 eq8 ch2eq8a1 0x000000 0x24 ch1eq8a2 0x000000 0x56 ch2eq8a2 0x000000 0x25 ch1eq8b1 0x000000 0x57 ch2e q8b1 0x000000 0x26 ch1eq8b2 0x000000 0x58 ch2eq8b2 0x000000 0x27 ch1eq8a0 0x200000 0x59 ch2eq8a0 0x200000 0x28 channel 1 eq9 ch1eq9a1 0x000000 0x5a channel 2 eq9 ch2eq9a1 0x000000 0x29 ch1eq9a2 0x000000 0x5b ch2eq9a2 0x000000 0x2a ch1eq9b1 0x 000000 0x5c ch2eq9b1 0x000000 0x2b ch1eq9b2 0x000000 0x5d ch2eq9b2 0x000000 0x2c ch1eq9a0 0x200000 0x5e ch2eq9a0 0x200000 0x2d channel 1 eq10 ch3eq1a1 0x000000 0x5f channel 2 eq10 ch3eq2a1 0x000000 0x2e ch3eq1a2 0x000000 0x60 ch3eq2a2 0x000000 0x2f ch3eq1b1 0x000000 0x61 ch3eq2b1 0x000000 0x30 ch3eq1b2 0x000000 0x62 ch3eq2b2 0x000000 0x31 ch3eq1a0 0x200000 0x63 ch3eq2a0 0x200000
IS31AP2111 integrated silicon solution, inc. ? www.issi.com 29 rev. 0 a, 09/ 10 /2014 table 30 user defined ram (continues) address name coefficient default 0x64 channel 1 mixer1 m11 0x7fffff 0x65 channel 1 mixer2 m12 0x000000 0x66 channel 2 mixer1 m21 0x000000 0x67 channel 2 mixer2 m22 0x7fffff 0x68~0x69 reserve reserve - 0x6a channel 1 prescale c1prs 0x7fffff 0x6b channel 2 prescale c2prs 0x7fffff 0x6c channel 1 postscale c1pos 0x7fff ff 0x6d channel 2 postscale c2pos 0x7fffff 0x6e reserve reserve - 0x6f ch1.2 power clipping pc1 0x200000 0x70 reserve reserve - 0x71 ch1.2 drc attack threshold drc1_ath 0x200000 0x72 ch1.2 drc release threshold drc1_rth 0x80000 0x73 ch3 drc attack t hreshold drc2_ath 0x200000 0x74 ch3 drc release threshold drc2_rth 0x80000 0x75 noise gate attack level ngal 0x0001a 0x76 noise gate release level ngrl 0x000053 0x77 drc1 energy coefficient drc1_ec 0x8000 0x78 drc2 energy coefficient drc2_ec 0x2000
IS31AP2111 integrated silicon solution, inc. ? www.issi.com 30 rev. 0 a, 09/ 10 /2014 classification reflow profiles profile feature pb - free assembly preheat & soak temperature min (tsmin) temperature max (tsmax) time (tsmin to tsmax) (ts) 150c 200c 60- 120 seconds average ramp - up rate (tsmax to tp) 3c/second max. liquidous temperature (tl) time at liquidous (tl) 217c 60- 150 seconds peak package body temperature (tp)* max 260c time (tp)** within 5c of the specified classification temperature (tc) max 30 seconds average ramp - down rate (tp to tsmax) 6c/second max. time 25c to pe ak temperature 8 minutes max. f igure 2 6 classification p rofile
IS31AP2111 integrated silicon solution, inc. ? www.issi.com 31 rev. 0 a, 09/ 10 /2014 package information e tssop - 2 4 note: all dimensions in millimeters unless otherwise stated.

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